Embodiments of the invention relate to a processor array, a fabric structure, a surface-covering structure and a method of transmitting electricity among a large number of processor elements arranged locally adjacent to one another.
In DE 101 58 784 A1, a processor array is described which has a large number of processor elements, each processor element having an image-generating element, such as a light-emitting diode, a memory, a plurality of data communication interfaces and a plurality of power supply interfaces.
The individual processor elements are arranged locally freely within the processor array and are coupled to their respectively immediately adjacent processor elements by means of their data communication interfaces for the purpose of exchanging electrical messages. The processor elements are connected to a common voltage source, the processor elements in each case being coupled to their immediately locally adjacent processor elements by means of their power supply interfaces.
Thus, a network of distributed processors or processor elements, which is fed from a common voltage supply, is described in DE 101 58 784 A1. Such a network is susceptible to electrical short-circuits occurring in the network. A single electrical short-circuit occurring within the context of the common voltage supply leads to the failure of the entire network of processor elements.
Furthermore, a method for the self-organization of the processor elements is described in DE 101 58 784 A1, that is to say substantially for the automatic determination of the position of the processor elements within the processor array in relation to a reference position. The determination of the respective position is carried out with a local exchange of electronic messages only between processor elements arranged immediately adjacent to one another.
A further problem in the network of processor elements described in DE 101 58 784 A1 but generally occurring in an arbitrary network of processor elements, is a synchronous driving of the processor elements in order to output information if the paths from an interface processor arranged at the reference position, which feeds data to all the processor elements of the processor array, are of different lengths.
DE 37 88 758 T2 discloses a polymorphic mesh network which has a network of processing elements and a program-controlled connection control mechanism in order to group the processing elements under program control. Each processing element is coupled to adjacent processing elements via connections.
DE 196 43 014 C1 discloses a bus system for electronic power supply, which has a voltage supply device for controlling the voltage supply to the bus system. The voltage supply device checks whether the voltage output has a sufficiently high resistance and controls the voltage supply of the bus system accordingly.
US 2003/0100837 A1 discloses a network of LED's which are fitted in clothing and coupled to one another.
As will be explained in more detail in the following text, even in the case of faulty processor elements within the processor array, the network of processor elements can still always operate in a functionally adequate manner in order to display symbols and sequences of symbols, for example text, arrows etc., but it is necessary for the faulty processor elements to be masked out within the context of the display of the symbols and sequences of symbols and the transmission of electronic messages which contain the information to be displayed by the image-generating elements. The routing paths have to be reformed around the faulty processor elements, routing paths being combined by means of routing branches. During the display of symbols and graphics, all the image points within a frame which are present in the network of image-generating elements and therefore in the network of processor elements must be driven synchronously.
Depending on the number of image points, the result is a data rate “number of image points contained in the image per second”.
These two above-described requirements lead to a very great broadband requirement on the data channels between the processor elements for transmitting the electronic messages with the symbols and graphics to be displayed. If some processor elements in the processor array fail and thus routing channels or routing paths have to be combined, then the data rate needed for the combined channels is additionally increased. Therefore, overdimensioning of the data transmission rate provided is required in order to provide the requisite bandwidth.